Design & Simulation of Cmos Inverter at Nanoscale beyond 20nm

The two major things, size and power consumption are very important parameter for any digital circuit design. Because all of us want to use the equipments that have compact in size and less power consumption, this paper investigates the applications of CMOS technology in the nanometer regime beyond 20 nm channel length where the relative study of average power dissipation of CMOS inverter is found in nano Watts. With the help of (H-spice) simulation tool, the simulation results are taken at different channel length (45nm 30nm, 20nm, 15nm) using CMOS technology. The results are analyzed at different supply voltages at constant load capacitance (CL =1fF) and values of various internal parameters of CMOS Inverter at different channel length are calculated.